fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.

Signed-off-by: Dave Liu <daveliu@freescale.com>