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(parent: 70415e1) | patch
riscv: cpu: fu740: clear feature disable CSR
authorGreen Wan <green.wan@sifive.com>
Thu, 27 May 2021 13:52:14 +0000 (06:52 -0700)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Mon, 31 May 2021 08:35:55 +0000 (16:35 +0800)
commitc552debbd8f2b852de669a7e30e8aa1aef4fa463
tree2859a73272d410809a08b040f804123ddf4d64b8tree | snapshot
parent70415e1e528db0856fedd4fa79b9f4a303a28c62commit | diff
riscv: cpu: fu740: clear feature disable CSR

Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
arch/riscv/cpu/fu740/spl.c diff | blob | history
My U-Boot fork