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(parent: 9502643) | patch
Some changes of TLB entry setting for MPC8572DS
authorHaiying Wang <Haiying.Wang@freescale.com>
Tue, 13 Jan 2009 21:29:28 +0000 (16:29 -0500)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 13 Jan 2009 22:58:46 +0000 (16:58 -0600)
commitb5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6
tree86bc278f77095fe7d3279605e972eb45007e976ctree | snapshot
parent950264317eb9594b2b5ee2fb65206200a1c6007acommit | diff
Some changes of TLB entry setting for MPC8572DS

- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
board/freescale/mpc8572ds/tlb.c diff | blob | history
include/configs/MPC8572DS.h diff | blob | history
My U-Boot fork