]> git.dujemihanovic.xyz Git - u-boot.git/commit
powerpc/b4860qds: Added Support for B4860QDS
authorYork Sun <yorksun@freescale.com>
Sun, 23 Dec 2012 19:25:27 +0000 (19:25 +0000)
committerAndy Fleming <afleming@freescale.com>
Wed, 30 Jan 2013 17:25:11 +0000 (11:25 -0600)
commitb5b06fb7b04a93ea48638d4d2ba1932051a28f64
tree1724bf4db2f33fecfe09628de1faec621b251391
parentdb9a807054ec82f4f6352677ea8b5d8176050a8a
powerpc/b4860qds: Added Support for B4860QDS

B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.

B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
  ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,  ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
  16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
  8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
  RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
  connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
  connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
  configuration reset source. The RCW source is set by appropriate
  DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
  DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
  - total four refclk, including CPRI clock scheme

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
13 files changed:
board/freescale/b4860qds/Makefile [new file with mode: 0644]
board/freescale/b4860qds/b4860qds.c [new file with mode: 0644]
board/freescale/b4860qds/b4860qds.h [new file with mode: 0644]
board/freescale/b4860qds/b4860qds_crossbar_con.h [new file with mode: 0644]
board/freescale/b4860qds/b4860qds_qixis.h [new file with mode: 0644]
board/freescale/b4860qds/ddr.c [new file with mode: 0644]
board/freescale/b4860qds/eth_b4860qds.c [new file with mode: 0644]
board/freescale/b4860qds/law.c [new file with mode: 0644]
board/freescale/b4860qds/pci.c [new file with mode: 0644]
board/freescale/b4860qds/tlb.c [new file with mode: 0644]
boards.cfg
doc/README.b4860qds [new file with mode: 0644]
include/configs/B4860QDS.h [new file with mode: 0644]