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ARM: AM43xx: Change DDR3 Reset Value
authorDave Gerlach <d-gerlach@ti.com>
Tue, 18 Feb 2014 12:32:01 +0000 (07:32 -0500)
committerTom Rini <trini@ti.com>
Tue, 4 Mar 2014 14:42:07 +0000 (09:42 -0500)
commitb56b9a0884afab53f7c93cd3c90648437ca7e35e
tree483c584aa38656dd0ac9a11ab7beffe8d886ee5ftree | snapshot
parentf84880f0f31e2d293b987d37446dc8a2e34aa925commit | diff
ARM: AM43xx: Change DDR3 Reset Value

The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value
of the ddr reset value for DDR3 before the EMIF takes over. We must have
this bit set high so that on exit from DeepSleep0 within the kernel the
reset line has the proper value.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
arch/arm/cpu/armv7/am33xx/emif4.c diff | blob | history
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