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armv8: fsl-layerscape: make icid setup endianness aware
authorLaurentiu Tudor <laurentiu.tudor@nxp.com>
Tue, 30 Jul 2019 14:29:57 +0000 (17:29 +0300)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Thu, 22 Aug 2019 03:37:36 +0000 (09:07 +0530)
commitaef654a2ed386d8bd53053383f6bf15ba016a79c
tree7dcfb1c5f8418120183dba9542a29eb74cb5f9e8tree | snapshot
parent08f9bc9f4332e13a4ba4705d84d62e41a45b3fbecommit | diff
armv8: fsl-layerscape: make icid setup endianness aware

The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/icid.c diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h diff | blob | history
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