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(parent: be2abe7) | patch
pci: pcie_dw_rockchip: Configure number of lanes and link width speed
authorJonas Karlman <jonas@kwiboo.se>
Wed, 2 Aug 2023 19:25:51 +0000 (19:25 +0000)
committerKever Yang <kever.yang@rock-chips.com>
Sat, 7 Oct 2023 02:23:12 +0000 (10:23 +0800)
commit9af0c7732bf1df29138bb63712dc3fcbc6d821af
treef38c0edb9ecb28236bf6903f73988be18d96c66atree | snapshot
parentbe2abe73df58a35da9e8d5afb13fccdf1b0faa8ecommit | diff
pci: pcie_dw_rockchip: Configure number of lanes and link width speed

Set number of lanes and link width speed control register based on the
num-lanes property.

Code imported almost 1:1 from dw_pcie_setup in mainline linux.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
drivers/pci/pcie_dw_rockchip.c diff | blob | history
My U-Boot fork