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ARC: Cache: Fix SLC operations when SLC is bypassed for data
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Wed, 21 Mar 2018 12:59:01 +0000 (15:59 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Wed, 21 Mar 2018 14:06:54 +0000 (17:06 +0300)
commit95336738f1cf2d4fabfc9bfc4981fa14714efc30
tree765031cfd5fec7bff551f623508e1f20aab0e45ftree | snapshot
parentc75eeb0bcbd5596f2b4e2b81eaa572675f019906commit | diff
ARC: Cache: Fix SLC operations when SLC is bypassed for data

If L1 D$ is disabled SLC is bypassed for data and all
load/store requests are sent directly to main memory.

If L1 I$ is disabled SLC is NOT bypassed for instructions
and all instruction requests are fetched through SLC.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
arch/arc/lib/cache.c diff | blob | history
My U-Boot fork