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(parent: 274fb46) | patch
clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock
authorPatrice Chotard <patrice.chotard@st.com>
Wed, 11 Apr 2018 15:07:45 +0000 (17:07 +0200)
committerTom Rini <trini@konsulko.com>
Tue, 8 May 2018 13:07:34 +0000 (09:07 -0400)
commit8b41464547330a39cc7e0ef87a5dd8f34db324e1
treeea0eb1eb7e28a3dba811bed5f1532a3acc2e296atree | snapshot
parent274fb461f4792431b3777874472c8bd6149e6168commit | diff
clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock

On all STM32F4 and F7 SoCs  family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>
drivers/clk/clk_stm32f.c diff | blob | history
drivers/misc/stm32_rcc.c diff | blob | history
include/stm32_rcc.h diff | blob | history
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