]> git.dujemihanovic.xyz Git - u-boot.git/commit
riscv : serial: use rx watermark to indicate rx data is present
authorSagar Shrikant Kadam <sagar.kadam@sifive.com>
Tue, 9 Jul 2019 12:23:44 +0000 (05:23 -0700)
committerAndes <uboot@andestech.com>
Thu, 15 Aug 2019 05:42:28 +0000 (13:42 +0800)
commit8836384c754295b1bbbb2910664c0d07de0dbde4
treeb648be5a4a39ff52d4573120d385a4f439091a3c
parentdf33f8646855e65b8e7232c7fd5739e1ae1eb58b
riscv : serial: use rx watermark to indicate rx data is present

In y-modem transfer mode, tstc/getc fail to check if there is any
data available / received in RX FIFO, and so y-modem transfer never
succeeds. Using receive watermark bit within ip register fixes the
issue.

This patch is based on commit c7392b7bc4e1 ("Use the RX watermark
interrupt pending bit for TSTC") available at[1]

[1] https://github.com/sifive/HiFive_U-Boot/tree/regression

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
drivers/serial/serial_sifive.c