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clk: zynqmp: Add set_rate support for gem rx and tsu clks
authorAshok Reddy Soma <ashok.reddy.soma@amd.com>
Wed, 19 Jul 2023 08:49:12 +0000 (02:49 -0600)
committerMichal Simek <michal.simek@amd.com>
Fri, 21 Jul 2023 07:00:39 +0000 (09:00 +0200)
commit7a480fd995e279dd883b9e4e24741f9c71d66143
tree846209b84de10786e055e7a6de55a74d5e9c89dbtree | snapshot
parent3fb4ef7d39abbb2f8f6cd349e4af11082bf8c8c4commit | diff
clk: zynqmp: Add set_rate support for gem rx and tsu clks

gem0_rx till gem3_rx  and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
drivers/clk/clk_zynqmp.c diff | blob | history
My U-Boot fork