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board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Sat, 8 Mar 2014 11:15:04 +0000 (16:45 +0530)
committerYork Sun <yorksun@freescale.com>
Wed, 23 Apr 2014 00:58:47 +0000 (17:58 -0700)
commit6b50f62cc4df7e2961fb45980cf91bb424ee263b
tree089b64c9c4d6bf24e0e030bdf5668b330658395btree | snapshot
parent59ff5d3306b9ac6d3afa0a249e17d8c14519e0cbcommit | diff
board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config

The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/b4860qds/b4_pbi.cfg diff | blob | history
My U-Boot fork