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(parent: 9070496) | patch
riscv: define a cache line size for the generic CPU
authorHeinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fri, 21 Jul 2023 16:01:18 +0000 (18:01 +0200)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Mon, 24 Jul 2023 05:22:24 +0000 (13:22 +0800)
commit6aabe229f8440c4960b904baf3aa33f692eea9a1
tree5a7314ebcc2d425d78126de4cd7eed11d716b5cetree | snapshot
parent90704967947817eecf6170daa3cea723e3110f8acommit | diff
riscv: define a cache line size for the generic CPU

The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
arch/riscv/cpu/generic/Kconfig diff | blob | history
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