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(parent: cf6ee11) | patch
riscv: cache: use CCTL to flush d-cache
authorRick Chen <rick@andestech.com>
Wed, 28 Aug 2019 10:46:11 +0000 (18:46 +0800)
committerAndes <uboot@andestech.com>
Tue, 3 Sep 2019 01:31:03 +0000 (09:31 +0800)
commit61ce84b2cf1a6672c8e402ce8174554b25629692
treeea53c8fd1dd9bf65bc1d29dd9a0957d060dc1917tree | snapshot
parentcf6ee112d802bc378172cfa5db3a430509cc82d8commit | diff
riscv: cache: use CCTL to flush d-cache

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/riscv/cpu/ax25/cache.c diff | blob | history
My U-Boot fork