]> git.dujemihanovic.xyz Git - u-boot.git/commit
clk: Check that composite clock's div has set_rate()
authorIgor Prusov <ivprusov@salutedevices.com>
Tue, 5 Dec 2023 23:23:33 +0000 (02:23 +0300)
committerSean Anderson <seanga2@gmail.com>
Fri, 15 Dec 2023 17:32:00 +0000 (12:32 -0500)
commit54d7da77306257a03231b04e7f2f9393ad7b0e46
tree1b4d6e2aca365574898eebae9e56892eebb6a184
parent3fb2d3d6acbaad50d2e638f6abb4e9d7a511c462
clk: Check that composite clock's div has set_rate()

It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it will cause NULL dereference during
clk_set_rate().

This patch adds rate_ops->set_rate check tp clk_composite_set_rate().

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231205232334.2931-2-ivprusov@salutedevices.com
drivers/clk/clk-composite.c