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(parent: de708da) | patch
board: ge: bx50v3: Setup LDB_DI_CLK source
authorAkshay Bhat <akshay.bhat@timesys.com>
Tue, 12 Apr 2016 22:13:58 +0000 (18:13 -0400)
committerStefano Babic <sbabic@denx.de>
Tue, 19 Apr 2016 14:05:13 +0000 (16:05 +0200)
commit494d43ec35ff3d27926ed9d668e0df4b7e6ae6d3
treee1462a832210defa82bfad1e6bfaea86a7c2eb74tree | snapshot
parentde708da0e87f39d99f902a5434702d6ba0f4c5e0commit | diff
board: ge: bx50v3: Setup LDB_DI_CLK source

To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
board/ge/bx50v3/bx50v3.c diff | blob | history
My U-Boot fork