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(parent: 64e8482) | patch
riscv: cache: support cache enable in SPL stage
authorZong Li <zong.li@sifive.com>
Thu, 14 Dec 2023 14:09:37 +0000 (14:09 +0000)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 27 Dec 2023 09:28:57 +0000 (17:28 +0800)
commit40c76dfed29ac2173bd32d730979ef2531029048
treee481fe5e4eed432724f4891497b7c026cef938ectree | snapshot
parent64e8482f1c94ab6e1fb4837a8744ca8a156c507ecommit | diff
riscv: cache: support cache enable in SPL stage

The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/lib/sifive_cache.c diff | blob | history
My U-Boot fork