]> git.dujemihanovic.xyz Git - u-boot.git/commit
board: sl28: fix RGMII clock and voltage
authorMichael Walle <michael@walle.cc>
Tue, 13 Apr 2021 15:54:17 +0000 (17:54 +0200)
committerPriyanka Jain <priyanka.jain@nxp.com>
Wed, 16 Jun 2021 12:44:08 +0000 (18:14 +0530)
commit2bf4658b8c5e5f4f43dc1888fe39ea61e6eeba64
tree5d7a650fc02ce859b34339005cbd3b3c9ecb78b0
parentfb4e64ef9daefba6c98e6a9620e28ffee741c075
board: sl28: fix RGMII clock and voltage

It was noticed that the clock isn't continuously enabled when there is
no link. This is because the 125MHz clock is derived from the internal
PLL which seems to go into some kind of power-down mode every once in a
while. The LS1028A expects a contiuous clock. Thus enable the PLL all
the time.

Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is
the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO
regulator.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts