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(parent: 98bc122) | patch
am33xx: Update DDR3 EMIF configuration sequence
authorTom Rini <trini@ti.com>
Tue, 26 Feb 2013 21:35:33 +0000 (16:35 -0500)
committerTom Rini <trini@ti.com>
Fri, 8 Mar 2013 21:41:12 +0000 (16:41 -0500)
commit1c382ead7a0081140e4961f2a03a20abd5e41f05
treed89e94e33fcdaf6780b7b675e38526eb263a5353tree | snapshot
parent98bc1228c800005e7addf95632e23079a236e5f5commit | diff
am33xx: Update DDR3 EMIF configuration sequence

Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence.  In our current (incorrect)
sequence some edge cases may fail to initalize correctly.

Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/am33xx/ddr.c diff | blob | history
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