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(parent: f97db54) | patch
85xx: Fix the clock adjust of mpc8569mds board
authorDave Liu <daveliu@freescale.com>
Fri, 27 Mar 2009 06:32:43 +0000 (14:32 +0800)
committerWolfgang Denk <wd@denx.de>
Tue, 9 Jun 2009 20:58:05 +0000 (22:58 +0200)
commit1b5291dddf5f16c7ae10e3cb165882fa96038b26
tree7ac021abc9b1e6f08dc64de6128868a28cabd175tree | snapshot
parentf97db54d7e773a32100247ee002686b6a014a87dcommit | diff
85xx: Fix the clock adjust of mpc8569mds board

Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>
board/freescale/mpc8569mds/ddr.c diff | blob | history
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