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(parent: 43bdb3b) | patch
pci: fsl: Do not access PCI BAR0 register of PCIe Root Port
authorPali Rohár <pali@kernel.org>
Tue, 2 May 2023 17:53:57 +0000 (19:53 +0200)
committerTom Rini <trini@konsulko.com>
Wed, 3 May 2023 22:30:46 +0000 (18:30 -0400)
commit0d734df4a459f01fdf1e62512fb28b28022cb6a9
tree91aabfe75c3f94edc285f9a3922917bf1042901etree | snapshot
parent43bdb3b39a0984c8c6ffcbb847bf648e941c0d26commit | diff
pci: fsl: Do not access PCI BAR0 register of PCIe Root Port

Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
PCIe Root Port does not have any PCIe memory, so returns zero when trying
to read from PCIe Root Port BAR0 and ignore any writes.

Signed-off-by: Pali Rohár <pali@kernel.org>
drivers/pci/pcie_fsl.c diff | blob | history
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