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riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
authorBin Meng <bmeng.cn@gmail.com>
Fri, 4 Jun 2021 05:51:12 +0000 (13:51 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 17 Jun 2021 01:39:08 +0000 (09:39 +0800)
commit048aff6d2621df2654dce6f833a2cf843358486a
treedaf0055c9f961f0a3dad8f9139e328364307bf10tree | snapshot
parentf050dd2b26abb4b107c3cdf7a5f5c420a9e1d4b6commit | diff
riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit

All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/dts/ae350_32.dts diff | blob | history
My U-Boot fork