From b04ed73a50fc03c7887f0b1887e11101e3b50a49 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 16 Dec 2015 10:42:29 +0900
Subject: [PATCH] ARM: uniphier: rename DTCR_RNKEN_* register bit to
DTCR_RANKEN_*
The bit 27-24 of the DTCR register is described as RANKEN in the
DDR PHY databook. Follow this abbreviation.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/ddrphy/ddrphy-training.c | 4 ++--
arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
index f1a2341d9c..b4d369a824 100644
--- a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
+++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
@@ -32,8 +32,8 @@ void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
/* Use Multi-Purpose Register for DQS gate training */
tmp |= DTCR_DTMPR;
/* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RNKEN_MASK;
- tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+ tmp &= ~DTCR_RANKEN_MASK;
+ tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
writel(tmp, p);
}
diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
index adcc972877..0c3b508821 100644
--- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
@@ -147,8 +147,8 @@ struct ddrphy {
#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */
-#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */
-#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT))
+#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
--
2.39.5