From 0b180d02a30191478ec8088661049e19930253f7 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 14 Feb 2017 17:40:21 +0100
Subject: [PATCH] arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
---
arch/arm/dts/zynq-7000.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 34fc6e5f89..f993e19ef2 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -38,6 +38,14 @@
};
};
+ fpga_full: fpga-full {
+ compatible = "fpga-region";
+ fpga-mgr = <&devcfg>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
--
2.39.5