From 0678587fb6f517d40c461f1d43fe7a6ff430f168 Mon Sep 17 00:00:00 2001 From: Stephen Warren <swarren@nvidia.com> Date: Tue, 26 Feb 2013 12:28:27 +0000 Subject: [PATCH] ARM: implement some Cortex-A9 errata workarounds Various errata exist in the Cortex-A9 CPU, and may be worked around by setting some bits in a CP15 diagnostic register. Add code to implement the workarounds, enabled by new CONFIG_ options. This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S, and modified to remove the logic to conditionally apply the WAR (since we know exactly which CPU we're running on given the U-Boot configuration), and use r0 instead of r10 for consistency with the rest of U-Boot's cpu_init_cp15(). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> --- README | 10 ++++++++++ arch/arm/cpu/armv7/start.S | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/README b/README index d51ece946c..e45ae4a135 100644 --- a/README +++ b/README @@ -485,6 +485,16 @@ The following options need to be configured: Thumb2 this flag will result in Thumb2 code generated by GCC. + CONFIG_ARM_ERRATA_742230 + CONFIG_ARM_ERRATA_743622 + CONFIG_ARM_ERRATA_751472 + + If set, the workarounds for these ARM errata are applied early + during U-Boot startup. Note that these options force the + workarounds to be applied; no CPU-type/version detection + exists, unlike the similar options in the Linux kernel. Do not + set these options unless they apply! + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 6b59529d5d..30f02d3943 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15) orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache #endif mcr p15, 0, r0, c1, c0, 0 + +#ifdef CONFIG_ARM_ERRATA_742230 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 4 @ set bit #4 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_743622 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 6 @ set bit #6 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_751472 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 11 @ set bit #11 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) -- 2.39.5