From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Tue, 19 Jun 2012 07:24:56 +0000 (+0000)
Subject: mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
X-Git-Tag: v2025.01-rc5-pxa1908~17673^2~35^2~24^2~116
X-Git-Url: http://git.dujemihanovic.xyz/%7B%7B%20.Permalink%20%7D%7D?a=commitdiff_plain;h=f69b0653acf5482a94fa1ec9542165914e30e50c;p=u-boot.git

mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register

commit acc4959fc1 (Revert "i.MX28: Enable additional DRAM address bits")
broke mx28evk boot.

Fix it by properly adjusting the HW_DRAM_CTL29 register value.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
---

diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 6587c454fe..00cc0cc2fa 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -161,6 +161,20 @@ const iomux_cfg_t iomux_setup[] = {
 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
 };
 
+#define HW_DRAM_CTL29	(0x74 >> 2)
+#define CS_MAP		0xf
+#define COLUMN_SIZE	0x2
+#define ADDR_PINS	0x1
+#define APREBIT		0xa
+
+#define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
+					ADDR_PINS << 8 | APREBIT)
+
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+}
+
 void board_init_ll(void)
 {
 	mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));