From: Michal Simek <michal.simek@amd.com>
Date: Wed, 16 Nov 2022 10:59:19 +0000 (+0100)
Subject: arm64: zynqmp: Describe TI phy as ethernet-phy-id with reset on zcu106
X-Git-Tag: v2025.01-rc5-pxa1908~1204^2~6
X-Git-Url: http://git.dujemihanovic.xyz/%7B%7B%20%24style.RelPermalink%20%7D%7D?a=commitdiff_plain;h=38920451c71844e2da82b4def8111a541997d649;p=u-boot.git

arm64: zynqmp: Describe TI phy as ethernet-phy-id with reset on zcu106

zcu106 also connects ethernet phy reset via tca6416 chip as is done on
other evaluation boards. That's why describe this connection to make sure
that ethernet phy is reset before it's use.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/21ccd672b799b5858021f6059098a1247c311fae.1668596358.git.michal.simek@amd.com
---

diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 3e137676fe..4858b4d1f5 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -200,12 +200,19 @@
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			reg = <0xc>;
+			compatible = "ethernet-phy-id2000.a231";
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };