riscv: remove cache enablement in start.S

Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a9e193569287f981b45c90575c3c09b528f8259c..8e58f641f1b7f5436654e9d248d45ea5437257bb 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -210,10 +210,6 @@ wait_for_gd_init:
        bnez    s2, secondary_hart_loop
 #endif
 
-       /* Enable cache */
-       jal     icache_enable
-       jal     dcache_enable
-
 #ifdef CONFIG_DEBUG_UART
        jal     debug_uart_init
 #endif