ddr: marvell: a38x: import code change from upstream

commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.

Import this change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 34cc17091036d1494a993d83f7870046ba1360cf..0358f6287a8097d25f0621426a67c6e35c0862c9 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = {
        {0x15a4, 0x0, MASK_ALL_BITS},
        {0x15a8, 0x0, MASK_ALL_BITS},
        {0x15ac, 0x0, MASK_ALL_BITS},
+       {0x1600, 0x0, MASK_ALL_BITS},
        {0x1604, 0x0, MASK_ALL_BITS},
        {0x1608, 0x0, MASK_ALL_BITS},
        {0x160c, 0x0, MASK_ALL_BITS},
@@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
                val = ((cl_mask_table[cl_value] & 0x1) << 2) |
                        ((cl_mask_table[cl_value] & 0xe) << 3);
 
+               cs_mask[0] = 0xc;
+
                CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
                        val, (0x7 << 4) | (0x1 << 2)));