video: tegra20: dc: add PLLD2 parent support

T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.

Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Ion Agorria <ion@agorria.com> # HTC One X
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 0e94e665efc2a2e5117c465211c6b0f3ed3f4b56..56a23b3c97975425996a9c209365ea98a72f2d4e 100644 (file)
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -304,6 +304,12 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
        if (priv->dc_clk[1] == CLOCK_ID_DISPLAY)
                rate /= 2;
 
+#ifndef CONFIG_TEGRA20
+       /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */
+       if (priv->dc_clk[1] == CLOCK_ID_DISPLAY2)
+               rate /= 2;
+#endif
+
        /*
         * HOST1X is init by default at 150MHz with PLLC as parent
         */