From f4d14c55504ce40287321bd63ee269e3233ee4ae Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 13 Oct 2008 15:15:31 +0200
Subject: [PATCH] ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command
for PLL setup
Signed-off-by: Stefan Roese <sr@denx.de>
---
board/amcc/canyonlands/bootstrap.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c
index 6b74743550..b1f4a213d9 100644
--- a/board/amcc/canyonlands/bootstrap.c
+++ b/board/amcc/canyonlands/bootstrap.c
@@ -40,6 +40,8 @@
static char *config_labels[] = {
"CPU: 600 PLB: 200 OPB: 100 EBC: 100",
"CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ "CPU:1066 PLB: 266 OPB: 88 EBC: 88",
NULL
};
@@ -54,6 +56,16 @@ static u8 boot_configs[][17] = {
0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08,
0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
+ {
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, 0x40, 0x08,
+ 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, 0x40, 0x08,
+ 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
{
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
--
2.39.5