From 9d8f814beb7f1857e814a42ec8362323ed88bdcc Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam <dinesh.maniyam@intel.com> Date: Fri, 15 Dec 2023 15:15:19 +0800 Subject: [PATCH] clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0) MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation but it is wrongly defined as BIT[7] in u-boot code. This register is used to hold associated pingpong counter in reset while PLL and 5:1 mux configuration is changed. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com> --- drivers/clk/altera/clk-mem-n5x.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/altera/clk-mem-n5x.h b/drivers/clk/altera/clk-mem-n5x.h index 7b687012e8..c6bc44bb34 100644 --- a/drivers/clk/altera/clk-mem-n5x.h +++ b/drivers/clk/altera/clk-mem-n5x.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* - * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2023 Intel Corporation <www.intel.com> */ #ifndef _CLK_MEM_N5X_ @@ -77,7 +77,7 @@ #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 -#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) +#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(0) #define MEMCLKMGR_EXTCNTRST_ALLCNTRST \ (MEMCLKMGR_EXTCNTRST_C0CNTRST) -- 2.39.5