From: Heesub Shin <heesub@gmail.com>
Date: Sun, 28 Apr 2024 14:24:02 +0000 (+0900)
Subject: ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey
X-Git-Url: http://git.dujemihanovic.xyz/%7B%7B%20%24style.Permalink%20%7D%7D?a=commitdiff_plain;h=2ae44edf1d341db1a0102150e02f463c90d657a0;p=u-boot.git

ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey

Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
125, 62.5 and 62.5Mhz in respectively.

Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
---

diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
index b780dbd95e..d07fdcf4bc 100644
--- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
@@ -115,11 +115,11 @@
 		bootph-all;
 	};
 
-	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+	/* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
 	pll4: st,pll@3 {
 		compatible = "st,stm32mp1-pll";
 		reg = <3>;
-		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+		cfg = < 3 124 5 9 9 PQR(1,1,1) >;
 		bootph-all;
 	};
 };