u32 sdr_timing;
};
+static struct dwmci_exynos_priv_data *exynos_dwmmc_get_priv(
+ struct dwmci_host *host)
+{
+#ifdef CONFIG_DM_MMC
+ return container_of(host, struct dwmci_exynos_priv_data, host);
+#else
+ return host->priv;
+#endif
+}
+
/*
* Function used as callback function to initialise the
* CLKSEL register for every mmc channel.
*/
static int exynos_dwmci_clksel(struct dwmci_host *host)
{
-#ifdef CONFIG_DM_MMC
- struct dwmci_exynos_priv_data *priv =
- container_of(host, struct dwmci_exynos_priv_data, host);
-#else
- struct dwmci_exynos_priv_data *priv = host->priv;
-#endif
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+
dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
return 0;
static void exynos_dwmci_board_init(struct dwmci_host *host)
{
- struct dwmci_exynos_priv_data *priv = host->priv;
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
dwmci_writel(host, EMMCP_MPSBEGIN0, 0);