+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774A1_PD_CA57_CPU0 0
-#define R8A774A1_PD_CA57_CPU1 1
-#define R8A774A1_PD_CA53_CPU0 5
-#define R8A774A1_PD_CA53_CPU1 6
-#define R8A774A1_PD_CA53_CPU2 7
-#define R8A774A1_PD_CA53_CPU3 8
-#define R8A774A1_PD_CA57_SCU 12
-#define R8A774A1_PD_A3VC 14
-#define R8A774A1_PD_3DG_A 17
-#define R8A774A1_PD_3DG_B 18
-#define R8A774A1_PD_CA53_SCU 21
-#define R8A774A1_PD_A2VC0 25
-#define R8A774A1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774A1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774B1_PD_CA57_CPU0 0
-#define R8A774B1_PD_CA57_CPU1 1
-#define R8A774B1_PD_A3VP 9
-#define R8A774B1_PD_CA57_SCU 12
-#define R8A774B1_PD_A3VC 14
-#define R8A774B1_PD_3DG_A 17
-#define R8A774B1_PD_3DG_B 18
-#define R8A774B1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774B1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774C0_PD_CA53_CPU0 5
-#define R8A774C0_PD_CA53_CPU1 6
-#define R8A774C0_PD_A3VC 14
-#define R8A774C0_PD_3DG_A 17
-#define R8A774C0_PD_3DG_B 18
-#define R8A774C0_PD_CA53_SCU 21
-#define R8A774C0_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774C0_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774E1_PD_CA57_CPU0 0
-#define R8A774E1_PD_CA57_CPU1 1
-#define R8A774E1_PD_CA57_CPU2 2
-#define R8A774E1_PD_CA57_CPU3 3
-#define R8A774E1_PD_CA53_CPU0 5
-#define R8A774E1_PD_CA53_CPU1 6
-#define R8A774E1_PD_CA53_CPU2 7
-#define R8A774E1_PD_CA53_CPU3 8
-#define R8A774E1_PD_A3VP 9
-#define R8A774E1_PD_CA57_SCU 12
-#define R8A774E1_PD_A3VC 14
-#define R8A774E1_PD_3DG_A 17
-#define R8A774E1_PD_3DG_B 18
-#define R8A774E1_PD_3DG_C 19
-#define R8A774E1_PD_3DG_D 20
-#define R8A774E1_PD_CA53_SCU 21
-#define R8A774E1_PD_3DG_E 22
-#define R8A774E1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774E1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7790_PD_CA15_CPU0 0
-#define R8A7790_PD_CA15_CPU1 1
-#define R8A7790_PD_CA15_CPU2 2
-#define R8A7790_PD_CA15_CPU3 3
-#define R8A7790_PD_CA7_CPU0 5
-#define R8A7790_PD_CA7_CPU1 6
-#define R8A7790_PD_CA7_CPU2 7
-#define R8A7790_PD_CA7_CPU3 8
-#define R8A7790_PD_CA15_SCU 12
-#define R8A7790_PD_SH_4A 16
-#define R8A7790_PD_RGX 20
-#define R8A7790_PD_CA7_SCU 21
-#define R8A7790_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7790_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7791_PD_CA15_CPU0 0
-#define R8A7791_PD_CA15_CPU1 1
-#define R8A7791_PD_CA15_SCU 12
-#define R8A7791_PD_SH_4A 16
-#define R8A7791_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7791_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Cogent Embedded Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7792_PD_CA15_CPU0 0
-#define R8A7792_PD_CA15_CPU1 1
-#define R8A7792_PD_CA15_SCU 12
-#define R8A7792_PD_SGX 20
-#define R8A7792_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7792_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- *
- * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
- */
-
-#define R8A7793_PD_CA15_CPU0 0
-#define R8A7793_PD_CA15_CPU1 1
-#define R8A7793_PD_CA15_SCU 12
-#define R8A7793_PD_SH_4A 16
-#define R8A7793_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7793_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7794_PD_CA7_CPU0 5
-#define R8A7794_PD_CA7_CPU1 6
-#define R8A7794_PD_SH_4A 16
-#define R8A7794_PD_SGX 20
-#define R8A7794_PD_CA7_SCU 21
-
-/* Always-on power area */
-#define R8A7794_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7795_PD_CA57_CPU0 0
-#define R8A7795_PD_CA57_CPU1 1
-#define R8A7795_PD_CA57_CPU2 2
-#define R8A7795_PD_CA57_CPU3 3
-#define R8A7795_PD_CA53_CPU0 5
-#define R8A7795_PD_CA53_CPU1 6
-#define R8A7795_PD_CA53_CPU2 7
-#define R8A7795_PD_CA53_CPU3 8
-#define R8A7795_PD_A3VP 9
-#define R8A7795_PD_CA57_SCU 12
-#define R8A7795_PD_CR7 13
-#define R8A7795_PD_A3VC 14
-#define R8A7795_PD_3DG_A 17
-#define R8A7795_PD_3DG_B 18
-#define R8A7795_PD_3DG_C 19
-#define R8A7795_PD_3DG_D 20
-#define R8A7795_PD_CA53_SCU 21
-#define R8A7795_PD_3DG_E 22
-#define R8A7795_PD_A3IR 24
-#define R8A7795_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7795_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7796_PD_CA57_CPU0 0
-#define R8A7796_PD_CA57_CPU1 1
-#define R8A7796_PD_CA53_CPU0 5
-#define R8A7796_PD_CA53_CPU1 6
-#define R8A7796_PD_CA53_CPU2 7
-#define R8A7796_PD_CA53_CPU3 8
-#define R8A7796_PD_CA57_SCU 12
-#define R8A7796_PD_CR7 13
-#define R8A7796_PD_A3VC 14
-#define R8A7796_PD_3DG_A 17
-#define R8A7796_PD_3DG_B 18
-#define R8A7796_PD_CA53_SCU 21
-#define R8A7796_PD_A3IR 24
-#define R8A7796_PD_A2VC0 25
-#define R8A7796_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7796_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2019 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77961_PD_CA57_CPU0 0
-#define R8A77961_PD_CA57_CPU1 1
-#define R8A77961_PD_CA53_CPU0 5
-#define R8A77961_PD_CA53_CPU1 6
-#define R8A77961_PD_CA53_CPU2 7
-#define R8A77961_PD_CA53_CPU3 8
-#define R8A77961_PD_CA57_SCU 12
-#define R8A77961_PD_CR7 13
-#define R8A77961_PD_A3VC 14
-#define R8A77961_PD_3DG_A 17
-#define R8A77961_PD_3DG_B 18
-#define R8A77961_PD_CA53_SCU 21
-#define R8A77961_PD_A3IR 24
-#define R8A77961_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77961_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- * Copyright (C) 2016 Glider bvba
- */
-
-#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77965_PD_CA57_CPU0 0
-#define R8A77965_PD_CA57_CPU1 1
-#define R8A77965_PD_A3VP 9
-#define R8A77965_PD_CA57_SCU 12
-#define R8A77965_PD_CR7 13
-#define R8A77965_PD_A3VC 14
-#define R8A77965_PD_3DG_A 17
-#define R8A77965_PD_3DG_B 18
-#define R8A77965_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77965_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Cogent Embedded Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77970_PD_CA53_CPU0 5
-#define R8A77970_PD_CA53_CPU1 6
-#define R8A77970_PD_CA53_SCU 21
-#define R8A77970_PD_A2IR0 23
-#define R8A77970_PD_A3IR 24
-#define R8A77970_PD_A2IR1 27
-#define R8A77970_PD_A2DP 28
-#define R8A77970_PD_A2CN 29
-#define R8A77970_PD_A2SC0 30
-#define R8A77970_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77970_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77980_PD_A2SC2 0
-#define R8A77980_PD_A2SC3 1
-#define R8A77980_PD_A2SC4 2
-#define R8A77980_PD_A2DP0 3
-#define R8A77980_PD_A2DP1 4
-#define R8A77980_PD_CA53_CPU0 5
-#define R8A77980_PD_CA53_CPU1 6
-#define R8A77980_PD_CA53_CPU2 7
-#define R8A77980_PD_CA53_CPU3 8
-#define R8A77980_PD_A2CN 10
-#define R8A77980_PD_A3VIP0 11
-#define R8A77980_PD_A2IR5 12
-#define R8A77980_PD_CR7 13
-#define R8A77980_PD_A2IR4 15
-#define R8A77980_PD_CA53_SCU 21
-#define R8A77980_PD_A2IR0 23
-#define R8A77980_PD_A3IR 24
-#define R8A77980_PD_A3VIP1 25
-#define R8A77980_PD_A3VIP2 26
-#define R8A77980_PD_A2IR1 27
-#define R8A77980_PD_A2IR2 28
-#define R8A77980_PD_A2IR3 29
-#define R8A77980_PD_A2SC0 30
-#define R8A77980_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77980_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77990_PD_CA53_CPU0 5
-#define R8A77990_PD_CA53_CPU1 6
-#define R8A77990_PD_CR7 13
-#define R8A77990_PD_A3VC 14
-#define R8A77990_PD_3DG_A 17
-#define R8A77990_PD_3DG_B 18
-#define R8A77990_PD_CA53_SCU 21
-#define R8A77990_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77990_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77995_PD_CA53_CPU0 5
-#define R8A77995_PD_CA53_SCU 21
-
-/* Always-on power area */
-#define R8A77995_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779A0_PD_A1E0D0C0 0
-#define R8A779A0_PD_A1E0D0C1 1
-#define R8A779A0_PD_A1E0D1C0 2
-#define R8A779A0_PD_A1E0D1C1 3
-#define R8A779A0_PD_A1E1D0C0 4
-#define R8A779A0_PD_A1E1D0C1 5
-#define R8A779A0_PD_A1E1D1C0 6
-#define R8A779A0_PD_A1E1D1C1 7
-#define R8A779A0_PD_A2E0D0 16
-#define R8A779A0_PD_A2E0D1 17
-#define R8A779A0_PD_A2E1D0 18
-#define R8A779A0_PD_A2E1D1 19
-#define R8A779A0_PD_A3E0 20
-#define R8A779A0_PD_A3E1 21
-#define R8A779A0_PD_3DG_A 24
-#define R8A779A0_PD_3DG_B 25
-#define R8A779A0_PD_A1CNN2 32
-#define R8A779A0_PD_A1DSP0 33
-#define R8A779A0_PD_A2IMP01 34
-#define R8A779A0_PD_A2DP0 35
-#define R8A779A0_PD_A2CV0 36
-#define R8A779A0_PD_A2CV1 37
-#define R8A779A0_PD_A2CV4 38
-#define R8A779A0_PD_A2CV6 39
-#define R8A779A0_PD_A2CN2 40
-#define R8A779A0_PD_A1CNN0 41
-#define R8A779A0_PD_A2CN0 42
-#define R8A779A0_PD_A3IR 43
-#define R8A779A0_PD_A1CNN1 44
-#define R8A779A0_PD_A1DSP1 45
-#define R8A779A0_PD_A2IMP23 46
-#define R8A779A0_PD_A2DP1 47
-#define R8A779A0_PD_A2CV2 48
-#define R8A779A0_PD_A2CV3 49
-#define R8A779A0_PD_A2CV5 50
-#define R8A779A0_PD_A2CV7 51
-#define R8A779A0_PD_A2CN1 52
-#define R8A779A0_PD_A3VIP0 56
-#define R8A779A0_PD_A3VIP1 57
-#define R8A779A0_PD_A3VIP2 58
-#define R8A779A0_PD_A3VIP3 59
-#define R8A779A0_PD_A3ISP01 60
-#define R8A779A0_PD_A3ISP23 61
-
-/* Always-on power area */
-#define R8A779A0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779F0_PD_A1E0D0C0 0
-#define R8A779F0_PD_A1E0D0C1 1
-#define R8A779F0_PD_A1E0D1C0 2
-#define R8A779F0_PD_A1E0D1C1 3
-#define R8A779F0_PD_A1E1D0C0 4
-#define R8A779F0_PD_A1E1D0C1 5
-#define R8A779F0_PD_A1E1D1C0 6
-#define R8A779F0_PD_A1E1D1C1 7
-#define R8A779F0_PD_A2E0D0 16
-#define R8A779F0_PD_A2E0D1 17
-#define R8A779F0_PD_A2E1D0 18
-#define R8A779F0_PD_A2E1D1 19
-#define R8A779F0_PD_A3E0 20
-#define R8A779F0_PD_A3E1 21
-
-/* Always-on power area */
-#define R8A779F0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779G0_PD_A1E0D0C0 0
-#define R8A779G0_PD_A1E0D0C1 1
-#define R8A779G0_PD_A1E0D1C0 2
-#define R8A779G0_PD_A1E0D1C1 3
-#define R8A779G0_PD_A2E0D0 16
-#define R8A779G0_PD_A2E0D1 17
-#define R8A779G0_PD_A3E0 20
-#define R8A779G0_PD_A33DGA 24
-#define R8A779G0_PD_A23DGB 25
-#define R8A779G0_PD_A1DSP0 33
-#define R8A779G0_PD_A2IMP01 34
-#define R8A779G0_PD_A2PSC 35
-#define R8A779G0_PD_A2CV0 36
-#define R8A779G0_PD_A2CV1 37
-#define R8A779G0_PD_A1CNN0 41
-#define R8A779G0_PD_A2CN0 42
-#define R8A779G0_PD_A3IR 43
-#define R8A779G0_PD_A1DSP1 45
-#define R8A779G0_PD_A2IMP23 46
-#define R8A779G0_PD_A2DMA 47
-#define R8A779G0_PD_A2CV2 48
-#define R8A779G0_PD_A2CV3 49
-#define R8A779G0_PD_A1DSP2 53
-#define R8A779G0_PD_A1DSP3 54
-#define R8A779G0_PD_A3VIP0 56
-#define R8A779G0_PD_A3VIP1 57
-#define R8A779G0_PD_A3VIP2 58
-#define R8A779G0_PD_A3ISP0 60
-#define R8A779G0_PD_A3ISP1 61
-#define R8A779G0_PD_A3DUL 62
-
-/* Always-on power area */
-#define R8A779G0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
-#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779H0_PD_A1E0D0C0 0
-#define R8A779H0_PD_A1E0D0C1 1
-#define R8A779H0_PD_A1E0D0C2 2
-#define R8A779H0_PD_A1E0D0C3 3
-#define R8A779H0_PD_A2E0D0 16
-#define R8A779H0_PD_A3CR0 21
-#define R8A779H0_PD_A3CR1 22
-#define R8A779H0_PD_A3CR2 23
-#define R8A779H0_PD_A33DGA 24
-#define R8A779H0_PD_A23DGB 25
-#define R8A779H0_PD_C4 31
-#define R8A779H0_PD_A1DSP0 33
-#define R8A779H0_PD_A2IMP01 34
-#define R8A779H0_PD_A2PSC 35
-#define R8A779H0_PD_A2CV0 36
-#define R8A779H0_PD_A2CV1 37
-#define R8A779H0_PD_A3IMR0 38
-#define R8A779H0_PD_A3IMR1 39
-#define R8A779H0_PD_A3VC 40
-#define R8A779H0_PD_A2CN0 42
-#define R8A779H0_PD_A1CN0 44
-#define R8A779H0_PD_A1DSP1 45
-#define R8A779H0_PD_A2DMA 47
-#define R8A779H0_PD_A2CV2 48
-#define R8A779H0_PD_A2CV3 49
-#define R8A779H0_PD_A3IMR2 50
-#define R8A779H0_PD_A3IMR3 51
-#define R8A779H0_PD_A3PCI 52
-#define R8A779H0_PD_A2PCIPHY 53
-#define R8A779H0_PD_A3VIP0 56
-#define R8A779H0_PD_A3VIP2 58
-#define R8A779H0_PD_A3ISP0 60
-#define R8A779H0_PD_A3DUL 62
-
-/* Always-on power area */
-#define R8A779H0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */
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