andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND

Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND
to do cache flush operation in M-mode and S-mode.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c
index 7d3df8722dd0e1d9e63eced941a2bd48d7e2feee..bb57498d75adab96dbc3c2c7f9e1a10a2261412e 100644 (file)
--- a/arch/riscv/cpu/andes/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -43,9 +43,7 @@ static void cache_ops(int (*ops)(struct udevice *dev))
 
 void flush_dcache_all(void)
 {
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
-#endif
+       csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)

diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 028fd01c2f385ae52cc199f33ca426d0ef16f6e5..7d6104a24e584b4fdf1e7dc0b3d60eb18d03b2d8 100644 (file)
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -12,7 +12,7 @@
 
 #define CSR_MCACHE_CTL 0x7ca
 #define CSR_MMISC_CTL 0x7d0
-#define CSR_MCCTLCOMMAND 0x7cc
+#define CSR_UCCTLCOMMAND 0x80c
 
 /* mcache_ctl register */