From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Date: Wed, 23 Nov 2022 09:04:51 +0000 (-0700)
Subject: spi: zynqmp_gqspi: Update tapdelay value
X-Git-Tag: v2025.01-rc5-pxa1908~1195^2~12
X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/login.html?a=commitdiff_plain;h=a5e770b21ccc4d3ffc5cf50cab481cb0e35ee6ce;p=u-boot.git

spi: zynqmp_gqspi: Update tapdelay value

The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1
tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1
based on the recommended value in IP spec.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 48eff777df..83a5c8aebf 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -94,7 +94,7 @@
 
 #define GQSPI_BAUD_DIV_SHIFT		2
 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT	5
-#define GQSPI_LPBK_DLY_ADJ_DLY_1	0x2
+#define GQSPI_LPBK_DLY_ADJ_DLY_1	0x1
 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT	3
 #define GQSPI_LPBK_DLY_ADJ_DLY_0	0x3
 #define GQSPI_USE_DATA_DLY		0x1