From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Date: Thu, 22 Nov 2018 10:26:23 +0000 (+0100)
Subject: riscv: implement the invalidate_icache_* functions
X-Git-Tag: v2025.01-rc5-pxa1908~3269^2~18
X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/html/index.html?a=commitdiff_plain;h=62a09ad53b7cb18bb47dc3c77155f56b894a6df5;p=u-boot.git

riscv: implement the invalidate_icache_* functions

Implement the functions invalidate_icache_range() and
invalidate_icache_all().

RISC-V does not have instructions for explicit cache-control. The
functions in this patch are implemented with the memory ordering
instruction for synchronizing the instruction and data streams. This may
be implemented as a cache flush or invalidate on simple processors,
others may only invalidate the relevant cache lines.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---

diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index 1d67c49c2c..d642a38a07 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -12,6 +12,16 @@ void flush_dcache_range(unsigned long start, unsigned long end)
 
 void invalidate_icache_range(unsigned long start, unsigned long end)
 {
+	/*
+	 * RISC-V does not have an instruction for invalidating parts of the
+	 * instruction cache. Invalidate all of it instead.
+	 */
+	invalidate_icache_all();
+}
+
+void invalidate_icache_all(void)
+{
+	asm volatile ("fence.i" ::: "memory");
 }
 
 void invalidate_dcache_range(unsigned long start, unsigned long end)