From 3e731aaba30c7011edf6391072eee845ed1b816f Mon Sep 17 00:00:00 2001 From: Dave Liu <daveliu@freescale.com> Date: Wed, 16 Dec 2009 10:24:39 -0600 Subject: [PATCH] fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 3be7e22710..adc4f6ee37 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1197,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* Don't set up boundaries for other CS * other than CS0, if bank interleaving * is enabled and not CS2+CS3 interleaved. + * But we need to set the ODT_RD_CFG and + * ODT_WR_CFG for CS1_CONFIG here. */ + set_csn_config(i, ddr, popts, dimm_params); break; } -- 2.39.5