From 1005ccda97243bcdbf31216685885cfd4ea32f29 Mon Sep 17 00:00:00 2001 From: Chris Kuethe <chris.kuethe@gmail.com> Date: Tue, 2 Jun 2015 16:31:43 -0700 Subject: [PATCH] patch - arm - define SYS_CACHELINE_SIZE for mx5 mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/include/asm/arch-mx5/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f664..5f0e1e6346 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@ #define ARCH_MXC +#define CONFIG_SYS_CACHELINE_SIZE 64 + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 -- 2.39.5