From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 29 Nov 2018 09:31:02 +0000 (+0100)
Subject: ARM: zynq: Wire SPL configuration for cse nor/nand targets
X-Git-Tag: v2025.01-rc5-pxa1908~3250^2~15
X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/git-logo.png?a=commitdiff_plain;h=fdba86972f23cab99710e19a04f36f170d1870e0;p=u-boot.git

ARM: zynq: Wire SPL configuration for cse nor/nand targets

These symlinks are here only for testing purpose where SPL is used
for soc configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/board/xilinx/zynq/zynq-cse-nand b/board/xilinx/zynq/zynq-cse-nand
new file mode 120000
index 0000000000..9d89a9957e
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-nand
@@ -0,0 +1 @@
+zynq-zc770-xm011
\ No newline at end of file
diff --git a/board/xilinx/zynq/zynq-cse-nor b/board/xilinx/zynq/zynq-cse-nor
new file mode 120000
index 0000000000..bb80693eab
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-nor
@@ -0,0 +1 @@
+zynq-zc770-xm012
\ No newline at end of file