From: Tien Fong Chee Date: Wed, 27 Apr 2022 04:27:21 +0000 (+0800) Subject: ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/git-logo.png?a=commitdiff_plain;h=ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4;p=u-boot.git ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee --- diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 7460f8c220..07a0f9f2ae 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -53,7 +53,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0xF #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f