From: Ruslan Bilovol Date: Thu, 1 Mar 2018 01:15:48 +0000 (+0200) Subject: watchdog: omap_wdt: improve watchdog reset path X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/git-logo.png?a=commitdiff_plain;h=87c692cbc17bc987c8a5f8c0377d8326348786ea;p=u-boot.git watchdog: omap_wdt: improve watchdog reset path Remove busy looping during watchdog reset. Each polling of W_PEND_WTGR bit ("finish posted write") after watchdog reset takes 120-140us on BeagleBone Black board. Current U-Boot code has watchdog resets in random places and often there is situation when watchdog is reset few times in a row in nested functions. This adds extra delays and slows the whole system. Instead of polling W_PEND_WTGR bit, we skip watchdog reset if the bit is set. Anyway, watchdog is in the middle of reset *right now*, so we can just return. This noticeably increases performance of the system. Below are some measurements on BBB: - DFU upload over USB 15% faster - fastboot image upload 3x times faster - USB ep0 transfers with 4k packets 20% faster Signed-off-by: Ruslan Bilovol Tested-by: Sam Protsenko Reviewed-by: Lokesh Vutla Reviewed-by: Lukasz Majewski Tested-by: Alex Kiernan --- diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7b1f429432..d724c964ed 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -53,16 +53,25 @@ void hw_watchdog_reset(void) { struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; - /* wait for posted write to complete */ - while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) - ; + /* + * Somebody just triggered watchdog reset and write to WTGR register + * is in progress. It is resetting right now, no need to trigger it + * again + */ + if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) + return; wdt_trgr_pattern = ~wdt_trgr_pattern; writel(wdt_trgr_pattern, &wdt->wdtwtgr); - /* wait for posted write to complete */ - while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR)) - ; + /* + * Don't wait for posted write to complete, i.e. don't check + * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to + * WTGR register outside of this func, and if entering it + * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset + * was just triggered. This prevents us from wasting time in busy + * polling of WDT_WWPS_PEND_WTGR bit. + */ } static int omap_wdt_set_timeout(unsigned int timeout)