From: Jonas Karlman Date: Fri, 26 Jan 2024 22:14:52 +0000 (+0000) Subject: rockchip: rk3588: Sync device tree with linux v6.7 X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/git-logo.png?a=commitdiff_plain;h=7c3e42b6132fcd0f390e136b19b0c024c1ac6f7c;p=u-boot.git rockchip: rk3588: Sync device tree with linux v6.7 Sync rk3588 device tree from linux v6.7. Also drop the rockchip,rk3568-dwc3 compatible now that dwc3-generic driver support the rockchip,rk3588-dwc3 compatible. Signed-off-by: Jonas Karlman --- diff --git a/arch/arm/dts/rk3588-turing-rk1.dtsi b/arch/arm/dts/rk3588-turing-rk1.dtsi index 9570b34aca..d88c0e8523 100644 --- a/arch/arm/dts/rk3588-turing-rk1.dtsi +++ b/arch/arm/dts/rk3588-turing-rk1.dtsi @@ -235,13 +235,13 @@ &pinctrl { fan { fan_int: fan-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; hym8563 { hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 31046fc7fe..992f7b5d66 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -7,7 +7,7 @@ / { usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; interrupts = ; clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts index 8f399c4317..e3a839a12d 100644 --- a/arch/arm/dts/rk3588s-orangepi-5.dts +++ b/arch/arm/dts/rk3588s-orangepi-5.dts @@ -38,7 +38,7 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 =<&leds_gpio>; + pinctrl-0 = <&leds_gpio>; led-1 { gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi index 63151d9d23..30db12c4fc 100644 --- a/arch/arm/dts/rk3588s-pinctrl.dtsi +++ b/arch/arm/dts/rk3588s-pinctrl.dtsi @@ -369,7 +369,7 @@ emmc_data_strobe: emmc-data-strobe { rockchip,pins = /* emmc_data_strobe */ - <2 RK_PA2 1 &pcfg_pull_none>; + <2 RK_PA2 1 &pcfg_pull_down>; }; }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index c0fd16c402..ebee2131ce 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -22,7 +22,7 @@ }; usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc000000 0x0 0x400000>; interrupts = ; clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, @@ -43,33 +43,6 @@ status = "disabled"; }; - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - pmu1_grf: syscon@fd58a000 { - bootph-all; - compatible = "rockchip,rk3588-pmu1-grf", "syscon"; - reg = <0x0 0xfd58a000 0x0 0x2000>; - }; - usbdpphy0_grf: syscon@fd5c8000 { compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; reg = <0x0 0xfd5c8000 0x0 0x4000>; @@ -206,6 +179,10 @@ status = "okay"; }; +&pmu1grf { + bootph-all; +}; + &scmi { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 61a9a11c3b..8aa0499f9b 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -443,6 +443,32 @@ status = "disabled"; }; + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; @@ -1329,6 +1355,16 @@ }; }; + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = , + , + , + ; + rockchip,pmu = <&pmu1grf>; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c index e8772d3a38..7b2cf37d9d 100644 --- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c @@ -10,7 +10,7 @@ static const struct udevice_id rk3588_syscon_ids[] = { { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF }, - { .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3588-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF }, { .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF }, { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },