clk: clk-imx8mn: Update clock tree and support set parent

Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocks

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 2d8e373131b77e5196c254cc5195370bb35cc986..a11b17f1672bc1d817bcc169bb96dd9da9a82c90 100644 (file)
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -81,6 +81,17 @@ static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_p
 static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
                                             "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
 
+#ifndef CONFIG_SPL_BUILD
+static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
+                                            "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+                                              "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
+                                            "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+#endif
+
 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
                                               "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
 
@@ -108,6 +119,9 @@ static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_
 static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
                                           "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
 
+static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
+                                          "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
+
 static ulong imx8mn_clk_get_rate(struct clk *clk)
 {
        struct clk *c;
@@ -165,11 +179,33 @@ static int imx8mn_clk_enable(struct clk *clk)
        return __imx8mn_clk_enable(clk, 1);
 }
 
+static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       struct clk *c, *cp;
+       int ret;
+
+       debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+       ret = clk_get_by_id(clk->id, &c);
+       if (ret)
+               return ret;
+
+       ret = clk_get_by_id(parent->id, &cp);
+       if (ret)
+               return ret;
+
+       ret = clk_set_parent(c, cp);
+       c->dev->parent = cp->dev;
+
+       return ret;
+}
+
 static struct clk_ops imx8mn_clk_ops = {
        .set_rate = imx8mn_clk_set_rate,
        .get_rate = imx8mn_clk_get_rate,
        .enable = imx8mn_clk_enable,
        .disable = imx8mn_clk_disable,
+       .set_parent = imx8mn_clk_set_parent,
 };
 
 static int imx8mn_clk_probe(struct udevice *dev)
@@ -340,6 +376,8 @@ static int imx8mn_clk_probe(struct udevice *dev)
        clk_dm(IMX8MN_CLK_USDHC3,
               imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
                                   base + 0xbc80));
+       clk_dm(IMX8MN_CLK_QSPI,
+              imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
 
        clk_dm(IMX8MN_CLK_I2C1_ROOT,
               imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -363,6 +401,24 @@ static int imx8mn_clk_probe(struct udevice *dev)
               imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
        clk_dm(IMX8MN_CLK_USDHC3_ROOT,
               imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+       clk_dm(IMX8MN_CLK_QSPI_ROOT,
+              imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+
+       /* clks not needed in SPL stage */
+#ifndef CONFIG_SPL_BUILD
+       clk_dm(IMX8MN_CLK_ENET_REF,
+              imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+              base + 0xa980));
+       clk_dm(IMX8MN_CLK_ENET_TIMER,
+              imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+              base + 0xaa00));
+       clk_dm(IMX8MN_CLK_ENET_PHY_REF,
+              imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+              base + 0xaa80));
+       clk_dm(IMX8MN_CLK_ENET1_ROOT,
+              imx_clk_gate4("enet1_root_clk", "enet_axi",
+              base + 0x40a0, 0));
+#endif
 
 #ifdef CONFIG_SPL_BUILD
        struct clk *clkp, *clkp1;