arm64: dts: rockchip: add thermal zones information on RK3588

This includes the necessary device tree data to allow thermal
monitoring on RK3588(s) using the on-chip TSADC device, along with
trip points for automatic thermal management.

Each of the CPU clusters (one for the little cores and two for
the big cores) get a passive cooling trip point at 85C, which
will trigger DVFS throttling of the respective cluster upon
reaching a high temperature condition.

All zones also have a critical trip point at 115C, which will
trigger a reset.

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 510cd9e688453166b2bff3999ed21cac97385bb5 ]

(cherry picked from commit 33e7079543d5eee1415b937054e8634000d1bde4)
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
index 629049f3dc16f935f2b8bf0041b4bdd839b153b9..78bc9dc97044d2247f37be50f3675fca1c6f027c 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/ata/ahci.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
        compatible = "rockchip,rk3588";
@@ -2368,6 +2369,158 @@
                status = "disabled";
        };
 
+       thermal_zones: thermal-zones {
+               /* sensor near the center of the SoC */
+               package_thermal: package-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 0>;
+
+                       trips {
+                               package_crit: package-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               /* sensor between A76 cores 0 and 1 */
+               bigcore0_thermal: bigcore0-thermal {
+                       polling-delay-passive = <100>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 1>;
+
+                       trips {
+                               bigcore0_alert: bigcore0-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               bigcore0_crit: bigcore0-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&bigcore0_alert>;
+                                       cooling-device =
+                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               /* sensor between A76 cores 2 and 3 */
+               bigcore2_thermal: bigcore2-thermal {
+                       polling-delay-passive = <100>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 2>;
+
+                       trips {
+                               bigcore2_alert: bigcore2-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               bigcore2_crit: bigcore2-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&bigcore2_alert>;
+                                       cooling-device =
+                                               <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               /* sensor between the four A55 cores */
+               little_core_thermal: littlecore-thermal {
+                       polling-delay-passive = <100>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 3>;
+
+                       trips {
+                               littlecore_alert: littlecore-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               littlecore_crit: littlecore-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&littlecore_alert>;
+                                       cooling-device =
+                                               <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               /* sensor near the PD_CENTER power domain */
+               center_thermal: center-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 4>;
+
+                       trips {
+                               center_crit: center-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               gpu_thermal: gpu-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 5>;
+
+                       trips {
+                               gpu_crit: gpu-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               npu_thermal: npu-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 6>;
+
+                       trips {
+                               npu_crit: npu-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+               };
+       };
+
        tsadc: tsadc@fec00000 {
                compatible = "rockchip,rk3588-tsadc";
                reg = <0x0 0xfec00000 0x0 0x400>;