ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding

According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Incorrect configuration of this bit does indeed cause sporadic
memory instability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>

diff --git a/board/aries/ma5d4evk/ma5d4evk.c b/board/aries/ma5d4evk/ma5d4evk.c
index 81463712fa828641fb4048f740836401280ece96..dd74e29b8ea4dea0f69a71cea3ca64e582e56125 100644 (file)
--- a/board/aries/ma5d4evk/ma5d4evk.c
+++ b/board/aries/ma5d4evk/ma5d4evk.c
@@ -349,7 +349,6 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
                    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
                    ATMEL_MPDDRC_CR_NB_8BANKS |
                    ATMEL_MPDDRC_CR_NDQS_DISABLED |
-                   ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
                    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 
        ddr2->rtr = 0x2b0;