clk: zynq: Add dummy clock enable function

A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index bf32d8317ab2f4df22045640d5dede49e32a1e3d..1f71b7d1e4f6269c6b9c8d4528072aec2210015b 100644 (file)
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -444,11 +444,21 @@ static ulong zynq_clk_get_rate(struct clk *clk)
 }
 #endif
 
+static int dummy_enable(struct clk *clk)
+{
+       /*
+        * Add implementation but by default all clocks are enabled
+        * after power up which is only one supported case now.
+        */
+       return 0;
+}
+
 static struct clk_ops zynq_clk_ops = {
        .get_rate = zynq_clk_get_rate,
 #ifndef CONFIG_SPL_BUILD
        .set_rate = zynq_clk_set_rate,
 #endif
+       .enable = dummy_enable,
 };
 
 static int zynq_clk_probe(struct udevice *dev)

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index d9ad0ff199d715dfa7b46afc9ede8616223a74b8..b79c4021b6a592f92db0333e478d74c4c713fb18 100644 (file)
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -577,7 +577,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
        debug("%s: CLK %ld\n", __func__, clock);
 
        ret = clk_enable(&clk);
-       if (ret && ret != -ENOSYS) {
+       if (ret) {
                dev_err(dev, "failed to enable clock\n");
                return ret;
        }

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 585c06d6bd87f11cf28d5572b2676a05a763eda3..a2a01112018f331ee810af5bcd25ad709421cb25 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -477,13 +477,13 @@ static int zynq_gem_init(struct udevice *dev)
        }
 
        ret = clk_set_rate(&priv->clk, clk_rate);
-       if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+       if (IS_ERR_VALUE(ret)) {
                dev_err(dev, "failed to set tx clock rate\n");
                return ret;
        }
 
        ret = clk_enable(&priv->clk);
-       if (ret && ret != -ENOSYS) {
+       if (ret) {
                dev_err(dev, "failed to enable tx clock\n");
                return ret;
        }

diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 2883e2466f8b43d2705e97512b801a429bb85244..799d5240473c3705fec27693fd6de4b94edda5e4 100644 (file)
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -127,7 +127,7 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
        debug("%s: CLK %ld\n", __func__, clock);
 
        ret = clk_enable(&clk);
-       if (ret && ret != -ENOSYS) {
+       if (ret) {
                dev_err(dev, "failed to enable clock\n");
                return ret;
        }

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 845f2d2f5f41ab1594c8960546fc90239db8191c..29dbbf55577677e70ba0bd1901f35b1db52ffc80 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -193,7 +193,7 @@ static int zynq_qspi_probe(struct udevice *bus)
        }
 
        ret = clk_enable(&clk);
-       if (ret && ret != -ENOSYS) {
+       if (ret) {
                dev_err(bus, "failed to enable clock\n");
                return ret;
        }

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 2971e55f41b101bb965cae30773d4bcf86ec7415..650d4d71d925563b0db041b670ff57f0bf7c90bb 100644 (file)
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -143,7 +143,7 @@ static int zynq_spi_probe(struct udevice *bus)
        }
 
        ret = clk_enable(&clk);
-       if (ret && ret != -ENOSYS) {
+       if (ret) {
                dev_err(bus, "failed to enable clock\n");
                return ret;
        }

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index c7db43a09a526d21e396282d7961dbb4a9f44cf9..bd25511aae6a1c410d1fb8c51e20f056dd6aefbc 100644 (file)
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -373,7 +373,7 @@ static int zynqmp_qspi_probe(struct udevice *bus)
        debug("%s: CLK %ld\n", __func__, clock);
 
        ret = clk_enable(&clk);
-       if (ret && ret != -ENOSYS) {
+       if (ret) {
                dev_err(bus, "failed to enable clock\n");
                return ret;
        }

diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c
index 9137d87697d454cd36dfd299471a21d8e356238c..11b30ae85df0142028dc164672a4e84c0d78d400 100644 (file)
--- a/drivers/watchdog/xilinx_wwdt.c
+++ b/drivers/watchdog/xilinx_wwdt.c
@@ -90,9 +90,8 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
        /* Calculate timeout count */
        count = timeout * clock_f;
 
-       /* clk_enable will return -ENOSYS when it is not implemented */
        ret = clk_enable(&wdt->clk);
-       if (ret && ret != -ENOSYS) {
+       if (ret) {
                dev_err(dev, "failed to enable clock\n");
                return ret;
        }