#include <asm/io.h>
#include <asm/pci.h>
#include <asm/arch/acpi.h>
+#include <asm/arch/hostbridge.h>
#include <asm/arch/systemagent.h>
#include <dt-bindings/sound/nhlt.h>
#include <dm/acpi.h>
TOLUD = 0xbc,
};
-/**
- * struct apl_hostbridge_plat - platform data for hostbridge
- *
- * @dtplat: Platform data for of-platdata
- * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
- * @early_pads_count: Number of pads to process
- * @pciex_region_size: BAR length in bytes
- * @bdf: Bus/device/function of hostbridge
- */
-struct apl_hostbridge_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dtd_intel_apl_hostbridge dtplat;
-#endif
- u32 *early_pads;
- int early_pads_count;
- uint pciex_region_size;
- pci_dev_t bdf;
-};
-
#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
static const struct nhlt_format_config dmic_1ch_formats[] = {
/* 48 KHz 16-bits per sample. */
#include <acpi/acpi_s3.h>
#include <asm/io.h>
#include <asm/pci.h>
+#include <asm/arch/pmc.h>
#include <linux/bitops.h>
#include <power/acpi_pmc.h>
CF9_GLB_RST = 1 << 20,
};
-struct apl_pmc_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dtd_intel_apl_pmc dtplat;
-#endif
- pci_dev_t bdf;
-};
-
static int apl_pmc_fill_power_state(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
/* This is needed by ACPI */
#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */
+#ifndef __ASSEMBLY__
+
+#include <dt-structs.h>
+
+/**
+ * struct apl_gpio_plat - platform data for each device
+ *
+ * @dtplat: of-platdata data from C struct
+ */
+struct apl_gpio_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_intel_apl_pinctrl dtplat;
+#endif
+};
+
+#endif /* __ASSEMBLY__ */
+
#endif /* _ASM_ARCH_GPIO_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef _ASM_ARCH_HOSTBRIDGE_H_
+#define _ASM_ARCH_HOSTBRIDGE_H_
+
+/**
+ * struct apl_hostbridge_plat - platform data for hostbridge
+ *
+ * @dtplat: Platform data for of-platdata
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_hostbridge dtplat;
+#endif
+ u32 *early_pads;
+ int early_pads_count;
+ uint pciex_region_size;
+ pci_dev_t bdf;
+};
+
+#endif /* _ASM_ARCH_HOSTBRIDGE_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef ASM_ARCH_PMC_H
+#define ASM_ARCH_PMC_H
+
+struct apl_pmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_pmc dtplat;
+#endif
+ pci_dev_t bdf;
+};
+
+#endif /* ASM_ARCH_PMC_H */
#include <asm-generic/gpio.h>
#include <asm/intel_pinctrl_defs.h>
-/**
- * struct apl_gpio_plat - platform data for each device
- *
- * @dtplat: of-platdata data from C struct
- */
-struct apl_gpio_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- /* Put this first since driver model will copy the data here */
- struct dtd_intel_apl_pinctrl dtplat;
-#endif
-};
-
static const struct reset_mapping rst_map[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },