*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &emmc;
- };
-};
-
&uart4 {
bootph-all;
clock-frequency = <24000000>;
- status = "okay";
+};
+
+&uart4_xfer {
+ bootph-all;
};
*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &emmc;
- };
+&gpio4 {
+ bootph-pre-ram;
};
&uart2 {
bootph-all;
clock-frequency = <24000000>;
- status = "okay";
+};
+
+&uart2m0_xfer {
+ bootph-all;
+};
+
+&vcc_sd {
+ bootph-pre-ram;
};
*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;
- };
+&emmc {
+ cap-sd-highspeed;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
};
-&uart0 {
- bootph-all;
-};
-
-&pinctrl {
+&emmc_bus4 {
+ bootph-pre-ram;
bootph-some-ram;
-
- uart0 {
- bootph-some-ram;
- };
- rtc {
- bootph-some-ram;
- };
};
-&uart0_xfer {
- bootph-some-ram;
+&uart0 {
+ bootph-all;
+ clock-frequency = <24000000>;
};
&uart0_cts {
- bootph-some-ram;
+ bootph-all;
};
&uart0_rts {
- bootph-some-ram;
+ bootph-all;
};
-&rtc_32k {
- bootph-some-ram;
+&uart0_xfer {
+ bootph-all;
};
mmc1 = &sdmmc;
};
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+
otp: nvmem@ff210000 {
compatible = "rockchip,rk3308-otp";
reg = <0x0 0xff210000 0x0 0x4000>;
};
&emmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&grf {
bootph-all;
};
-&sdmmc {
+&pcfg_pull_none {
bootph-all;
- u-boot,spl-fifo-mode;
};
-&grf {
+&pcfg_pull_none_4ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_none_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&pcfg_pull_up_4ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl {
bootph-all;
};
-&saradc {
+&rtc_32k {
bootph-all;
- status = "okay";
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_det {
+ bootph-pre-ram;
+ bootph-some-ram;
};
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply SPL_CLK
+ imply SPL_DM_SEQ_ALIAS
imply SPL_FIT_SIGNATURE
+ imply SPL_PINCTRL
imply SPL_RAM
imply SPL_REGMAP
imply SPL_ROCKCHIP_COMMON_BOARD
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y